NXP Semiconductors TV Converter Box TDA8752B User Manual

TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Rev. 03 — 21 July 2000  
Product specification  
1. General description  
The TDA8752B is a triple 8-bit ADC with controllable amplifiers and clamps for the  
digitizing of large bandwidth RGB signals.  
The clamp level, the gain and all other settings are controlled via a serial interface  
(either I2C-bus or 3-wire serial bus, selected via a logic input).  
The IC also includes a PLL that can be locked to the horizontal line frequency and  
generates the ADC clock. The PLL jitter is minimized for high resolution PC graphics  
applications. An external clock can also be input to the ADC.  
It is possible to set the TDA8752B serial bus address to four different values, when  
several TDA8752B ICs are used in a system, by means of the I2C-bus interface (for  
example, two ICs used in an odd/even configuration).  
2. Features  
Triple 8-bit ADC  
Sampling rate up to 110 Msps  
IC controllable via a serial interface, which can be either I2C-bus or 3-wire serial  
c
c
bus, selected via a TTL input pin  
IC analog voltage input from 0.4 to 1.2 V (p-p) to produce a full-scale ADC input of  
1 V (p-p)  
Three clamps for programming a clamping code between 63.5 and +64 in steps  
of 12 LSB for RGB signals, and from +120 to +136 in steps of 12 LSB for YUV  
signals  
Three controllable amplifiers: gain controlled via the serial interface to produce a  
full-scale resolution of 12 LSB peak-to-peak  
Amplifier bandwidth of 250 MHz  
Low gain variation with temperature  
PLL controllable via the serial interface to generate the ADC clock which can be  
locked to a line frequency of 15 to 280 kHz  
Integrated PLL divider  
Programmable phase clock adjustment cells  
Internal voltage regulators  
TTL compatible digital inputs and outputs  
Chip enable high-impedance ADC output  
 
   
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
Table 1: Quick reference data…continued  
Symbol  
DRPLL  
Ptot  
Parameter  
Conditions  
Min  
100  
Typ  
Max  
4095  
Unit  
PLL divider ratio  
total power dissipation  
fclk = 110 MHz; ramp input  
1.1  
112  
W
jPLL(rms)  
maximum PLL phase jitter  
(RMS value)  
fref = 66.67 kHz;  
fclk = 110 MHz  
ps  
5. Ordering information  
Table 2: Ordering information  
Type number  
Package  
Name  
Sampling  
frequency (MHz)  
Description  
Version  
TDA8752BH/8  
QFP100  
plastic quad flat package; 100 leads (lead length  
SOT317-2 110  
1.95 mm); body 14 × 20 × 2.8 mm  
9397 750 07338  
© Philips Electronics N.V. 2000. All rights reserved.  
Product specification  
Rev. 03 — 21 July 2000  
3 of 38  
 
 
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
6. Block diagram  
V
V
V
V
V
V
CLP  
AGND  
OGND AGND  
DGND  
CCA(R) CCA(B) CCO(R) CCO(B) CCA(PLL)  
SSD  
G
G
PLL  
V
V
V
V
V
AGND  
AGND  
OGND  
OGND OGND  
CCA(G)  
DDD  
CCO(G)  
CCD  
CCO(PLL)  
85  
R
B
R
B
PLL  
82  
11 19 27 40 79 69 59 95 99  
89  
13 21 29 41 70 60 48 96  
86  
9
7
6
RAGC  
RCLP  
RBOT  
8
RGAINC  
12  
10  
71 to 78  
45  
RIN  
CLAMP  
R0 to R7  
ROR  
RDEC  
MUX  
OUTPUTS  
ADC  
3
V
ref  
RED CHANNEL  
14  
16  
17  
15  
GAGC  
GCLP  
GBOT  
GGAINC  
61 to 68  
46  
20  
18  
GIN  
G0 to G7  
GOR  
GREEN CHANNEL  
GDEC  
87  
25  
23  
OE  
22  
24  
BAGC  
BCLP  
BBOT  
BGAINC  
49, 52 to 58  
47  
28  
26  
B0 to B7  
BOR  
BIN  
BLUE CHANNEL  
BDEC  
36  
TDO  
TCK  
84  
83  
CKADCO  
CKBO  
35  
34  
HSYNCI  
TDA8752B  
ADD2  
ADD1  
SEN  
SCL  
33  
38  
42  
39  
37  
32  
81  
80  
SERIAL  
CKAO  
INTERFACE  
2
CKREFO  
I C-BUS  
REGULATOR  
OR  
3-WIRE  
92  
91  
93  
94  
CKEXT  
INV  
PLL  
97  
SDA  
DIS  
2
I C-bus; 1-bit  
(Hlevel)  
2
COAST  
CKREF  
I C/3W  
1, 5, 30, 31, 43 , 44  
50, 51, 100  
90  
4
2
88  
98  
CZ  
FCE467  
n.c.  
HSYNC  
DEC1  
DEC2 PWDWN CP  
Fig 1. Block diagram.  
9397 750 07338  
© Philips Electronics N.V. 2000. All rights reserved.  
Product specification  
Rev. 03 — 21 July 2000  
 
4 of 38  
   
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
CLP  
RAGC  
RCLP  
CLAMP  
CONTROL  
V
P
DAC  
150  
kΩ  
CLKADC  
8
RIN  
AGC  
V
ADC  
REGISTER  
ROR  
MUX  
V
ref  
2
I C-bus: 8 bits (Or)  
3 kΩ  
8
CCAR  
OUTPUTS  
R0 to R7  
OE  
8
D
45 kΩ  
DAC  
D R  
R
8
7
RBOT  
5
1
REGISTER  
FINE GAIN ADJUST  
REGISTER  
COARSE GAIN ADJUST  
1
2
2
I C-bus: 5 bits (Fr)  
I C-bus: 7 bits (Cr)  
2
I C-BUS  
FCE468  
RGAINC  
HSYNCI  
Fig 2. Red channel diagram.  
9397 750 07338  
© Philips Electronics N.V. 2000. All rights reserved.  
Product specification  
Rev. 03 — 21 July 2000  
 
5 of 38  
 
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
C
C
P
Z
COAST  
CKEXT  
INV  
CZ  
CP  
2
I C-bus; 1 bit  
(Vlevel)  
12 to  
100 MHz  
loop filter  
I C-bus;  
2
CKREF  
PHASE  
3 bits (Z)  
VCO  
MUX  
0°/180°  
CKADCO  
FREQUENCY  
edge selector  
DETECTOR  
2
I C-bus;  
2
I C-bus;  
2 bits (Vco)  
1 bit  
(Edge)  
phase selector A  
I C-bus;  
5 bits (Pa)  
2
I C-bus; 5 bits  
2
CLKADC  
(Ip, Up, Do)  
2
I C-bus;  
1 bit (Cka)  
MUX  
MUX  
CKBO  
DIV N (100 to 4095)  
2
2
I C-bus; 12 bits (Di)  
I C-bus;  
phase selector B  
I C-bus; 5 bits (Pb)  
1 bit (Ckb)  
2
NCKBO  
CKAO  
2
I C-bus;  
1 bit (Ckab)  
SYNCHRO  
CKREFO  
FCE465  
Fig 3. PLL diagram.  
9397 750 07338  
© Philips Electronics N.V. 2000. All rights reserved.  
Product specification  
Rev. 03 — 21 July 2000  
 
6 of 38  
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
7. Pinning information  
7.1 Pinning  
n.c.  
1
2
3
4
5
6
7
8
9
CKREFO  
80  
79  
DEC2  
V
CCO(R)  
V
78 R7  
ref  
DEC1  
n.c.  
R6  
R5  
77  
76  
RAGC  
RBOT  
RGAINC  
RCLP  
75 R4  
R3  
R2  
R1  
74  
73  
72  
RDEC 10  
71 R0  
V
11  
OGND  
70  
69  
68  
CCA(R)  
R
RIN 12  
V
CCO(G)  
AGND  
13  
G7  
R
GAGC 14  
GBOT 15  
GGAINC 16  
GCLP 17  
67 G6  
G5  
G4  
G3  
66  
65  
64  
TDA8752BH  
GDEC 18  
63 G2  
V
19  
G1  
G0  
62  
61  
CCA(G)  
GIN 20  
AGND 21  
60 OGND  
G
G
BAGC 22  
BBOT 23  
BGAINC 24  
BCLP 25  
59  
58  
57  
V
CCO(B)  
B7  
B6  
56 B5  
55 B4  
BDEC 26  
V
27  
B3  
B2  
54  
53  
CCA(B)  
BIN 28  
AGND 29  
52 B1  
B
n.c. 30  
51 n.c.  
FCE469  
Fig 4. Pin configuration.  
9397 750 07338  
© Philips Electronics N.V. 2000. All rights reserved.  
Product specification  
Rev. 03 — 21 July 2000  
7 of 38  
 
   
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
7.2 Pin description  
Table 3: Pin description  
Symbol  
n.c.  
Pin  
1
Description  
not connected  
DEC2  
Vref  
2
main regulator decoupling input 2  
gain stabilizer voltage reference input  
main regulator decoupling input 1  
not connected  
3
DEC1  
n.c.  
4
5
RAGC  
RBOT  
RGAINC  
RCLP  
RDEC  
VCCA(R)  
RIN  
6
red channel AGC output  
7
red channel ladder decoupling input (BOT)  
red channel gain capacitor input  
red channel gain clamp capacitor input  
red channel gain regulator decoupling input  
red channel gain analog power supply  
red channel gain analog input  
red channel gain analog ground  
green channel AGC output  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
AGNDR  
GAGC  
GBOT  
GGAINC  
GCLP  
GDEC  
VCCA(G)  
GIN  
green channel ladder decoupling input (BOT)  
green channel gain capacitor input  
green channel gain clamp capacitor input  
green channel gain regulator decoupling input  
green channel gain analog power supply  
green channel gain analog input  
green channel gain analog ground  
blue channel AGC output  
AGNDG  
BAGC  
BBOT  
BGAINC  
BCLP  
BDEC  
VCCA(B)  
BIN  
blue channel ladder decoupling input (BOT)  
blue channel gain capacitor input  
blue channel gain clamp capacitor input  
blue channel gain regulator decoupling input  
blue channel gain analog power supply  
blue channel gain analog input  
blue channel gain analog ground  
not connected  
AGNDB  
n.c.  
n.c.  
I2C/3W  
not connected  
selection input between I2C-bus (active HIGH) and 3-wire  
serial bus (active LOW)  
ADD1  
ADD2  
TCK  
33  
34  
35  
36  
37  
I2C-bus address control input 1  
I2C-bus address control input 2  
scan test mode input (active HIGH)  
scan test output  
I2C-bus and 3-wire serial bus disable control input (disable at  
HIGH level)  
TDO  
DIS  
SEN  
38  
select enable for 3-wire serial bus input (see Figure 10)  
9397 750 07338  
© Philips Electronics N.V. 2000. All rights reserved.  
Product specification  
Rev. 03 — 21 July 2000  
 
8 of 38  
 
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
Table 3: Pin description…continued  
Symbol  
Pin  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
Description  
SDA  
VDDD  
VSSD  
SCL  
n.c.  
I2C-bus/3-wire serial bus data input  
logic I2C-bus/3-wire serial bus digital power supply  
logic I2C-bus/3-wire serial bus digital ground  
I2C-bus/3-wire serial bus clock input  
not connected  
n.c.  
not connected  
ROR  
GOR  
BOR  
OGNDB  
B0  
red channel ADC output bit out of range  
green channel ADC output bit out of range  
blue channel ADC output bit out of range  
blue channel ADC output ground  
blue channel ADC output bit 0 (LSB)  
not connected  
n.c.  
n.c.  
not connected  
B1  
blue channel ADC output bit 1  
blue channel ADC output bit 2  
blue channel ADC output bit 3  
blue channel ADC output bit 4  
blue channel ADC output bit 5  
blue channel ADC output bit 6  
blue channel ADC output bit 7 (MSB)  
blue channel ADC output power supply  
green channel ADC output ground  
green channel ADC output bit 0 (LSB)  
green channel ADC output bit 1  
green channel ADC output bit 2  
green channel ADC output bit 3  
green channel ADC output bit 4  
green channel ADC output bit 5  
green channel ADC output bit 6  
green channel ADC output bit 7 (MSB)  
green channel ADC output power supply  
red channel ADC output ground  
red channel ADC output bit 0 (LSB)  
red channel ADC output bit 1  
red channel ADC output bit 2  
red channel ADC output bit 3  
red channel ADC output bit 4  
red channel ADC output bit 5  
red channel ADC output bit 6  
red channel ADC output bit 7 (MSB)  
red channel ADC output power supply  
B2  
B3  
B4  
B5  
B6  
B7  
VCCO(B)  
OGNDG  
G0  
G1  
G2  
G3  
G4  
G5  
G6  
G7  
VCCO(G)  
OGNDR  
R0  
R1  
R2  
R3  
R4  
R5  
R6  
R7  
VCCO(R)  
9397 750 07338  
© Philips Electronics N.V. 2000. All rights reserved.  
Product specification  
Rev. 03 — 21 July 2000  
 
9 of 38  
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
Table 3: Pin description…continued  
Symbol  
Pin  
80  
Description  
CKREFO  
CKAO  
reference output clock re-synchronized horizontal pulse  
81  
PLL clock output 3 (in phase with reference output clock  
CKAO or CKBO)  
OGNDPLL  
CKBO  
82  
83  
84  
85  
86  
87  
PLL digital ground  
PLL clock output 2  
CKADCO  
VCCO(PLL)  
DGND  
PLL clock output 1 (in phase with internal ADC clock)  
PLL output power supply  
digital ground  
OE  
output enable; active LOW (when OE is HIGH, the outputs are  
in high-impedance)  
PWDWN  
88  
power-down control input (device is in Power-down mode  
when this pin is HIGH)  
CLP  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
clamp pulse input (clamp active HIGH)  
horizontal synchronization input pulse  
PLL clock output inverter command input (invert when HIGH)  
external clock input  
HSYNC  
INV  
CKEXT  
COAST  
CKREF  
VCCD  
PLL coast command input  
PLL reference clock input  
digital power supply  
AGNDPLL  
CP  
PLL analog ground  
PLL filter input  
CZ  
PLL filter input  
VCCA(PLL)  
n.c.  
PLL analog power supply  
not connected  
9397 750 07338  
© Philips Electronics N.V. 2000. All rights reserved.  
Product specification  
Rev. 03 — 21 July 2000  
 
10 of 38  
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
8. Functional description  
This triple high-speed 8-bit ADC is designed to convert RGB signals, coming from an  
analog source, into digital data used by a LCD driver (pixel clock up to 200 MHz when  
using 2 ICs).  
8.1 IC analog video inputs  
The video inputs are internally DC polarized. These inputs are AC coupled externally.  
8.2 Clamps  
Three independent parallel clamping circuits are used to clamp the video input  
signals on the black level and to control the brightness level. The clamping code is  
programmable between code 63.5 and +64 and from +120 to +136 in steps of  
12 LSB. The programming of the clamp value is achieved via an 8-bit DAC. Each  
clamp must be able to correct an offset from ±0.1 V to ±10 mV within 300 ns, and  
correct the total offset in 10 lines.  
The clamps are controlled by an external TTL positive going pulse (pin CLP). The  
drop of the video signal is <1 LSB.  
Normally, the circuit operates with a 0 code clamp, corresponding to the 0 ADC code.  
This clamp code can be changed from 63.5 to +64 as represented in Figure 5, in  
steps of 12 LSB. The digitized video signal is always between code 0 and code 255 of  
the ADC. It is also possible to clamp from code 120 to code 136 corresponding to  
120 ADC code to 136 ADC code. Then clamping on code 128 of the ADC is possible.  
255  
digitized  
video  
signal  
= 120 to 136  
code 64  
clamp  
code 0  
programming  
code63.5  
video signal  
CLP  
FCE471  
Fig 5. Clamp definition.  
8.3 Variable gain amplifiers  
Three independent variable gain amplifiers are used to provide, to each channel, a  
full-scale input range signal to the 8-bit ADC. The gain adjustment range is designed  
so that for an input range varying from 0.4 to 1.2 V (p-p), the output signal  
corresponds to the ADC full-scale input of 1 V (p-p).  
To ensure that the gain does not vary over the whole operating temperature range, an  
external supplied reference voltage Vref = 2.5 V (DC), with a maximum variation of  
100 ppm/°C, is used to calibrate the gain at the beginning of each video line before  
the clamp pulse.  
9397 750 07338  
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Product specification  
Rev. 03 — 21 July 2000  
11 of 38  
 
         
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
The calibration of the gains is done using the following principle.  
From the reference voltage Vref a reference signal of 0.156 V (p-p) (116Vref) is  
generated internally. During the synchronization part of the video line, the multiplexer,  
controlled by the TTL synchronization signal (HSYNCI, coming from HSYNC;  
see Figure 1) with a width equal to one of the video synchronization signals (e.g. the  
signal coming from a synchronization separator), is switched between the two  
amplifiers.  
The output of the multiplexer is either the normal video signal or the 0.156 V  
reference signal (during HSYNC).  
register. Depending on the result of the comparison, the gain of the variable gain  
amplifiers is adjusted (coarse gain control; see Figure 2 and 6). The three 7-bit  
registers receive data via a serial interface to enable the gain to be programmed.  
The preset value loaded in the 7-bit register is chosen between approximately  
67 codes to ensure the full-scale input range (see Figure 6). A contrast control can be  
achieved using these registers. In this case care should be taken to stay within the  
allowed code range (32 to 99).  
A fine correction using three 5-bit DACs, also controlled via the serial interface, is  
used to fine tune the gain of the three channels (fine gain control; see Figure 2 and 7)  
and to compensate the channel-to-channel gain mismatch.  
With a full-scale ADC input, the resolution of the fine register corresponds to 12 LSB  
peak-to-peak variation.  
To use these gain controls correctly, it is recommended to fix the coarse gain (to have  
a full-scale ADC input signal) to within 4 LSB and then adjust it with the fine gain. The  
gain is adjusted during HSYNC. During this time the output signal is not related to the  
amplified input signal. The outputs, when the coarse gain system is stable, are  
related to the programmed coarse code (see Figure 6).  
N
ADC output  
code  
COARSE  
code  
127  
255  
227  
G
G
(max)  
(min)  
99  
coarse  
register  
value  
(67 codes)  
32  
0
160  
128  
V
V
0.2  
0.6  
ref  
16  
i (p-p)  
0.156 =  
2
FCE472  
Fig 6. Coarse gain control.  
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Product specification  
Rev. 03 — 21 July 2000  
 
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TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
ADC  
output code  
G
NCOARSE  
255  
227  
G
G
(max)  
(min)  
coarse  
register  
value  
(67 codes)  
N
COARSE  
160  
128  
V
ref  
N
= 0  
FINE  
N
= 31  
FINE  
FCE473  
Fig 7. Fine gain correction for a coarse gain GNCOARSE  
.
8.4 ADCs  
The ADCs are 8-bit with a maximum clock frequency of 110 Msps. The ADCs input  
range is 1 V (p-p) full-scale. One out of range bit exists per channel (ROR, GOR and  
BOR). It will be at logic 1 when the signal is out of range of the full-scale of the ADCs.  
Pipeline delay in the ADCs is 1 clock cycle from sampling to data output.  
The ADCs reference ladders regulators are integrated.  
8.5 ADC outputs  
ADC outputs are straight binary. An output enable pin (OE; active LOW) enables the  
output status between active and high-impedance (OE = HIGH) to be switched; it is  
recommended to load the outputs with a 10 pF capacitive load. The timing must be  
checked very carefully if the capacitive load is more than 10 pF.  
8.6 Phase-locked loop  
The ADCs are clocked either by an internal PLL locked to the CKREF clock (all of the  
PLL is on-chip except the loop filter capacitance) or by an external clock applied to  
pin CKEXT. Selection is performed via the serial interface bus.  
The reference clock (CKREF) range is between 15 and 280 kHz. Consequently, the  
VCO minimum frequency is 12 MHz and the maximum frequency is 110 MHz. The  
gain of the VCO part can be controlled via the serial interface, depending on the  
frequency range to which the PLL is locked.  
To increase the bandwidth of the PLL, the charge pump current, controlled by the  
serial interface, must also be increased. The relationship between the frequency and  
the current is given by the following equation:  
KO IP  
(CZ + CP) ⋅ DR  
1
f n  
=
-------------------------------------  
(1)  
------  
2π  
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Product specification  
Rev. 03 — 21 July 2000  
 
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TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
Where:  
fn = the natural PLL frequency  
KO = the VCO gain  
DR = PLL divider ratio  
CZ and CP = capacitors of the PLL filter.  
The other PLL equation is as follows:  
f n  
1
1
2
f z  
=
and ξ =  
×
(2)  
-----------------------------  
2π × R × CZ  
-- -----  
f z  
Where:  
fz = loop filter zero frequency  
R = the chosen resistance for the filter  
ξ = the damping factor  
FO = 0 dB loop gain frequency.  
Different resistances for the filter can be programmed via the serial interface. To  
improve the performances, the PLL parameters should be chosen so that:  
2π × DR × FO  
FO = 2ξ ⋅ f n R IP  
=
(3)  
(4)  
----------------------------------  
KO  
FO  
0.3π × DR × f ref  
0.15 R I ≤  
= Lim  
---------  
-----------------------------------------  
P
f ref  
KO  
The values of R and IP must be chosen so that the product is the closest to Lim. In  
the event that there are several choices, the couple for which the ξ value is the closest  
to 1 must be chosen.  
A software program called “PLL calculator’” is available on Philips Semiconductor  
Internet site to calculate the best PLL parameters.  
It is possible to control (independently) the phase of the ADC clock and the phase of  
an additional clock output (which could be used to drive a second TDA8752B). For  
this, two serial interface-controlled digital phase-shift controllers are included  
(controlled by 5-bit registers, phase-shift controller steps are 11.25 deg each on the  
whole PLL frequency range).  
CKREF is re-synchronized, by the synchro block, on the CKAO clock. The output is  
CKREFO (LOW during 8 clock periods). CKAO is the clock at the output of the phase  
selector A. This clock can be used as the clocks for CKBO and CKADCO. The timing  
is given in Figure 8.  
Pin COAST is used to disconnect the PLL phase frequency detector during the frame  
flyback or the unavailability of the CKREF signal. This signal can normally be derived  
from the VSYNC signal.  
The clock output is able to drive an external 10 pF load (for the on-chip ADCs).  
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Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
The PLL can be used in three different methods:  
The IC can be used as stand-alone with a sampling frequency of up to 110 MHz.  
When an RGB signal is at a pixel frequency exceeding 100 to 200 MHz, it is  
possible to follow one of the two possibilities given below:  
Using one TDA8752B: the sampling rate can be reduced by a factor of two, by  
sampling the even pixels in the even frame and the odd pixels in the odd frame.  
Pin INV is used to toggle between the frames.  
Using two TDA8752Bs: the PLL of the master TDA8752B is used to drive both  
ADC clocks. The PLL of the slave TDA8752B is disconnected and the CKBO of  
the master TDA8752B is connected to pin CKEXT of the TDA8752B master and  
CKAO to the slave TDA8752B. In this case, on pin CKAO CKBO will be the  
output (with bit CKAB of the master at logic 1).  
The master TDA8752B is used to sample the even pixels and the slave  
TDA8752B for odd pixels, using a 180 deg phase shift between the clocks (both  
pins CKADCO). The master chip and the slave chip have their pin INV LOW,  
which guarantees the 180 deg shift ADC clock drive. It is then necessary to  
adjust phase B of the master chip. Special care should be taken with the quality  
of the input signal (input settling time).  
If CKREFO output signal at the master chip is needed, it is possible to use one  
of the two phase A values in order to avoid set-up and hold problems in the  
SYNCHRO function; e.g. PHASEA = 100000 and PHASEA = 111111.  
When INV is LOW, CKADCO is equal to CKEXT inverted.  
CKREF  
CKAO  
t
CKAO  
CKREFO  
FCE470  
t
CKREFO  
t
tCKAO = tCLK(buffer) + tphase selector [tCLK(buffer) = 10 ns and tphase selector  
=
phase selector × TCLK(pixel) ].  
--------------------------  
2π  
T
TCLK(pixel)  
tCKREFO = either tCKAO  
CLK(pixel) if PHASEA 01000 or t  
------------------------  
+
if PHASEA < 01000.  
------------------------  
CKAO  
2
2
Fig 8. Timing diagram.  
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Triple high-speed Analog-to-Digital Converter 110 Msps  
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COAST  
CKEXT  
INV  
12 to  
100 MHz  
MUX  
0 /180  
CKADCO  
CKBO  
phase selector A  
I C-bus;  
5 bits (Pa)  
2
2
CLKADC  
I C-bus;  
1 bit (Cka)  
(Cka = 1)  
MUX  
2
CKREF  
I C-bus;  
PLL  
phase selector B  
I C-bus; 5 bits (Pb)  
2
1 bit (Ckb)  
(Ckb = 1)  
NCKBO  
CKAO  
MUX  
Master TDA8752B  
2
(even pixels)  
I C-bus;  
1 bit (Ckab)  
(Ckab = 1)  
SYNCHRO  
CKEXT  
CKREFO  
INV  
COAST  
12 to  
100 MHz  
MUX  
0 /180  
CKADCO  
phase selector A  
2
2
I C-bus;  
CLKADC  
MUX  
I C-bus;  
1 bit (Cka)  
(Cka = 1)  
5 bits (Pa)  
CKBO  
CKREF  
2
I C-bus;  
phase selector B  
I C-bus; 5 bits (Pb)  
PLL  
2
1 bit (Ckb)  
(Ckb = 0)  
NCKBO  
CKAO  
MUX  
Slave TDA8752B  
2
I C-bus;  
1 bit (Ckab)  
(Ckab = 0)  
(odd pixels)  
SYNCHRO  
CKREFO  
FCE466  
Slave at 180 deg phase shift with respect to pin CKADCO of the master TDA8752B.  
Fig 9. Dual TDA8752B solution for pixel clock rate with a single phase adjustment (100 to 200 MHz).  
8.7 I2C-bus and 3-wire serial bus interface  
The I2C-bus and 3-wire serial buses control the status of the different control DACs  
and registers. Control pin DIS enables or disables the full serial interface function  
(disable at HIGH level). Four ICs can be used in the same system and programmed  
address respectively, for use with the I2C-bus interface. All programming is described  
in Section 9 “I2C-bus and 3-wire serial bus interfaces”.  
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TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
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9. I2C-bus and 3-wire serial bus interfaces  
9.1 Register definitions  
The configuration of the different registers is shown in Table 4.  
Table 4: I2C-bus and 3-wire serial bus registers  
Function Subaddress  
name  
Bit definition  
Default  
value  
A7 A6 A5 A4 A3 A2 A1 A0 MSB  
LSB  
SUBADDR −  
OFFSETR  
COARSER X  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
Mode Sa3 Sa2 Sa1 Sa0 XXX1 0000  
X
Or7  
Or8  
X
Or6  
Cr6  
X
Or5  
Cr5  
X
Or4  
Cr4  
Fr4  
Or3  
Cr3  
Fr3  
Or2 Or1 Or0 0111 1111  
Cr2 Cr1 Cr0 0010 0000  
FINER  
X
X
Fr2  
Fr1  
Fr0  
XXX0 0000  
OFFSETG  
Og7  
Og8  
X
Og6  
Cg6  
X
Og5  
Cg5  
X
Og4  
Cg4  
Fg4  
Ob4  
Cb4  
Fb4  
Og3 Og2 Og1 Og0 0111 1111  
Cg3 Cg2 Cg1 Cg0 0010 0000  
Fg3 Fg2 Fg1 Fg0 XXX0 0000  
Ob3 Ob2 Ob1 Ob0 0111 1111  
Cb3 Cb2 Cb1 Cb0 0010 0000  
Fb3 Fb2 Fb1 Fb0 XXX0 0000  
COARSEG X  
FINEG  
X
X
OFFSETB  
Ob7  
Ob8  
X
Ob6  
Cb6  
X
Ob5  
Cb5  
X
COARSEB X  
FINEB  
CONTROL X  
X
Vlevel Hlevel Edge Up  
Do  
Vco0 Di11 Di10 Di9  
Di4 Di3 Di2 Di1  
Ip2  
Ip1  
Ip0  
0000 0100  
0110 0001  
1001 0000  
VCO  
X
X
Z2  
Z1  
Z0  
Vco1  
Di5  
DIVIDER  
(LSB)  
Di8  
Di7  
Di6  
PHASEA  
PHASEB  
X
X
X
X
X
X
X
X
1
1
1
1
0
0
0
1
X
X
Di0  
Cka  
Pa4  
Pb4  
Pa3 Pa2 Pa1 Pa0 X000 0000  
Pb3 Pb2 Pb1 Pb0 X000 0000  
Ckab Ckb  
All the registers are defined by a subaddress of 8 bits; bit A4 refers to the mode which  
is used with the I2C-bus interface; bits Sa3 to Sa0 are the subaddresses of each  
register.  
Bit Mode, used only with the I2C-bus, enables two modes to be programmed:  
Mode 0  
Mode 1  
if bit Mode = 0, each register is programmed independently by giving its  
subaddress and its content  
if bit Mode = 1, all the registers are programmed one after the other by  
giving this initial condition (XXX1 1111) as the subaddress state; thus,  
the registers are charged following the predefined sequence of 16 bytes  
(from subaddress 0000 to 1101).  
9.1.1 Offset register  
This register controls the clamp level for the RGB channels. The relationship between  
the programming code and the level of the clamp code is given in Table 5.  
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Triple high-speed Analog-to-Digital Converter 110 Msps  
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Table 5: Coding  
Programmed code  
Clamp code  
ADC output  
0
63.5  
63  
62.5  
...  
underflow  
1
2
...  
127  
...  
0
0
...  
...  
254  
255  
256  
...  
63.5  
64  
63 or 64  
64  
120  
...  
120  
...  
287  
136  
136  
The default programmed value is:  
Programmed code = 127  
Clamp code = 0  
ADC output = 0.  
9.1.2 Coarse and fine registers  
These two registers enable the gain control, the AGC gain with the coarse register  
and the reference voltage with the fine register. The coarse register programming  
equation is as follows:  
NCOARSE + 1  
NCOARSE + 1  
--------------------------------------------------  
Vref (512 NFINE  
1
16  
GAIN =  
×
=
× 32  
(5)  
----------------------------------------------- -----  
)
NFINE  
Vref 1 –  
-----------------  
32 × 16  
Where: Vref = 2.5 V.  
The gain correspondence is given in Table 6. The gain is linear with reference to the  
programming code (NFINE = 0).  
Table 6: Gain correspondence (COARSE)  
NCOARSE  
32  
Gain  
0.825  
2.5  
Vi to be full-scale (V)  
1.212  
0.4  
99  
The default programmed value is as follows:  
N
COARSE = 32  
Gain = 0.825  
V to be full-scale = 1.212 V.  
i
To modulate this gain, the fine register is programmed using the above equation. With  
a full-scale ADC input, the fine register resolution is a 12 LSB peak-to-peak  
(see Table 7 for NCOARSE = 32).  
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Triple high-speed Analog-to-Digital Converter 110 Msps  
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Table 7: Gain correspondence (FINE)  
NFINE  
0
Gain  
0.825  
0.878  
Vi to be full-scale (V)  
1.212  
1.139  
31  
The default programmed value is: NFINE = 0.  
9.1.3 Control register  
COAST and HSYNC signals can be inverted by setting the I2C-bus control bits  
‘Vlevel’ and ‘Hlevel’ respectively. When ‘Vlevel’ and ‘Hlevel’ are set to zero  
respectively, COAST and HSYNC are active HIGH.  
The bit ‘Edge’ defines the rising or falling edge of CKREF to synchronize the PLL. It  
will be on the rising edge if the bit is at logic 0 and on the falling edge if the bit is at  
logic 1.  
The bits ‘Up’ and ‘Do’ are used for the test, to force the charge pump current. These  
bits have to be logic 0 during normal use.  
The bits ‘Ip0’, ‘Ip1’ and ‘Ip2’ control the charge pump current, to increase the  
bandwidth of the PLL, as shown in Table 8.  
Table 8: Charge pump current control  
Ip2  
0
Ip1  
0
Ip0  
0
Current (µA)  
6.25  
12.5  
25  
0
0
1
0
1
0
0
1
1
50  
1
0
0
100  
200  
400  
700  
1
0
1
1
1
0
1
1
1
The default programmed value is as follows:  
Charge pump current = 100 µA  
Test bits: no test mode; bits ‘Up’ and ‘Do’ at logic 0  
Rising edge of CKREF: bit ‘Edge’ at logic 0  
COAST and HSYNC inputs are active HIGH: bits ‘Vlevel’ and ‘Hlevel’ at logic 0.  
9.1.4 VCO register  
The bits ‘Z2’, ‘Z1’ and ‘Z0’ enable the internal resistance for the VCO filter to be  
selected.  
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Triple high-speed Analog-to-Digital Converter 110 Msps  
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Table 9: VCO register bits  
Z2  
0
Z1  
0
Z0  
0
Resistance (k)  
high impedance  
0
0
1
128  
32  
16  
8
0
1
0
0
1
1
1
0
0
1
0
1
4
1
1
0
2
1
1
1
1
Table 10: VCO gain control  
Vco1  
Vco0  
VCO gain (MHz/V)  
Pixel clock  
frequency range  
(MHz)  
0
0
1
1
0
1
0
1
15  
20  
35  
50  
10 to 20  
20 to 40  
40 to 70  
70 to 110  
The bits Vco1 and Vco0 control the VCO gain.  
The default programmed value is as follows:  
Internal resistance = 16 kΩ  
VCO gain = 15 MHz/V.  
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Triple high-speed Analog-to-Digital Converter 110 Msps  
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9.1.5 Divider register  
This register controls the PLL frequency. The bits are the LSB bits.  
The default programmed value is 0011 0010 0000 = 800.  
The MSB bits (Di11, Di10 and Di9) and the LSB bit (Di0) have to be programmed  
before bits ‘Di8’ to ‘Di1’ are programmed, to obtain the required divider ratio. Bit ‘Di0’  
is used for the parity divider number (bit ‘Di0’ = 0 means even number, while  
bit ‘Di0’ = 1 means odd number). It should be noted that if the I2C-bus programming is  
done in mode 1 (bit Mode = 1) and bit ‘Di0’ has to be toggled, then the registers have  
to be loaded twice to have the update divider ratio.  
9.1.6 Power-down mode  
When the supply is completely switched off, the registers are set to their default  
values; in that event they have to be reprogrammed if the required settings are  
different (e.g. through an EEPROM)  
When the device is in Power-down mode, the previously programmed register  
values remain unaffected.  
9.1.7 PHASEA and PHASEB registers  
Bit ‘Cka’ is logic 0 when the used clock is the PLL clock, and logic 1 when the used  
clock is the external clock.  
Bit ‘Ckb’ is logic 0 when the second clock is not used.  
Bits ‘Pa4’ to ‘Pa0’ and bits ‘Pb4’ to ‘Pb0’ are used to program the phase shift for the  
clock, CKADCO, CKAO and CKBO (see Table 11). Concerning the PHASEB register,  
bit ‘Ckab’ is used to have either CKAO or CKBO at pin CKAO (pin 81).  
Table 11: Phase registers bits  
Pa4 and Pb4 Pa3 and Pb3 Pa2 and Pb2 Pa1 and Pb1 Pa0 and Pb0 Phase shift (deg)  
0
0
...  
1
1
0
0
...  
1
1
0
0
...  
1
1
0
0
...  
1
1
0
1
...  
0
1
0
11.25  
...  
337.5  
348.75  
The default programmed value is as follows:  
No external clock: bit ‘Cka’ is logic 0  
No use of the second clock: bit ‘Ckb’ is logic 0  
Phase shift for CKAO and CKADCO is 0 deg  
Phase shift for CKBO is 0 deg  
Clock CKAO at pin CKAO: bit ‘Ckab’ is logic 0.  
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Triple high-speed Analog-to-Digital Converter 110 Msps  
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9.2 I2C-bus protocol  
Table 12: I2C-bus address  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
1
0
0
1
1
ADD2  
ADD1  
0
The I2C-bus address of the circuit is 1001 1xx0.  
Bits ‘A2’ and ‘A1’ are fixed by the potential on pins ADD1 and ADD2. Thus, four  
TDA8752Bs can be used on the same system, using the addresses for  
ADD1 and ADD2 with the I2C-bus. Bit ‘A0’ must always be equal to logic 0 because it  
is not possible to read the data in the register. The timing and protocol for the I2C-bus  
are standard. Two sequences are available, see Table 13 and 14.  
Table 13: Address sequence for mode 0  
Where: S = START condition, ACK = acknowledge and P = STOP condition.  
IC ADDRESS ACK SUBADDRESS ACK DATA  
REGISTER1 REGISTER1  
(see Table 4)  
S
ACK SUBADDRESS ACK ...  
REGISTER2  
P
P
Table 14: Address sequence for mode 1  
Where: S = START condition, ACK = acknowledge and P = STOP condition.  
IC ADDRESS ACK SUBADDRESS ACK DATA  
XXX1 1111 REGISTER1  
S
ACK DATA  
REGISTER2  
ACK ...  
(see Table 4)  
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9.3 3-wire serial bus protocol  
For the 3-wire serial bus the first byte refers to the register address which is programmed. The second byte refers to the  
data to be sent to the chosen register (see Table 4). The acquisition is achieved via SEN.  
Using the 3-wire serial bus interface, an indefinite number of ICs can operate on the same system. Pin SEN is used to  
validate the circuits.  
SEN  
SCL  
SDA  
t
= 600 ns  
100 ns  
r3W  
1
9
1
9
t
= 100 ns  
t
= 100 ns  
D7  
s3W  
h3W  
X
X
X
X
X
A3  
A2  
A1  
A0  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
X
FCE474  
Fig 10. 3-wire serial bus protocol.  
 
   
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
10. Limiting values  
Table 15: Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
VCCA  
Parameter  
Conditions  
Min  
Max  
+7.0  
+7.0  
+7.0  
+7.0  
Unit  
V
analog supply voltage  
digital supply voltage  
logic supply voltage  
output stages supply voltage  
supply voltage differences  
VCCA VCCD  
0.3  
0.3  
0.3  
0.3  
VCCD  
V
VDDD  
V
VCCO  
VCC  
V
1.0  
1.0  
1.0  
1.0  
0.3  
+1.0  
+1.0  
+1.0  
+1.0  
+7.0  
V
V
V
V
V
VCCO VCCD; VCCO VDDD  
VCCA VDDD; VCCD VDDD  
VCCA VCCO  
Vi(RGB)  
RGB input voltage range  
referenced  
to AGND  
Io  
output current  
10  
mA  
mA  
mA  
°C  
II(OE)  
II(PWDWN)  
Tstg  
input current pin OE  
input current pin PWDWN  
storage temperature  
ambient temperature  
junction temperature  
1.0  
1.0  
+150  
70  
55  
0
Tamb  
Tj  
°C  
150  
°C  
11. Thermal characteristics  
Table 16: Thermal characteristics  
Symbol  
Parameter  
Conditions  
Value  
Unit  
Rth(j-a)  
thermal resistance from junction to in free air  
ambient  
52  
K/W  
12. Characteristics  
Table 17: Characteristics  
VCCA = V11 (or V19, V27 or V99) referenced to AGND (V13, V21, V29 or V96) = 4.75 to 5.25 V; VCCD = V95 referenced to DGND  
(V86) = 4.75 to 5.25 V; VDDD = V40 referenced to VSSD (V41) = 4.75 to 5.25 V; VCCO = V59 (or V69, V79 or V85) referenced to  
OGND (V48, V60, V70 or V82) = 4.75 to 5.25 V; AGND, DGND, OGND and VSSD connected together; Tamb = 0 to 70 °C; typical  
values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise specified.  
Symbol  
Supplies  
VCCA  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
analog supply voltage  
digital supply voltage  
logic supply voltage  
4.75  
4.75  
4.75  
4.75  
5.0  
5.0  
5.0  
5.0  
5.25  
5.25  
5.25  
5.25  
V
V
V
V
VCCD  
VDDD  
VCCO  
output stages supply  
voltage  
ICCA  
analog supply current  
120  
mA  
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Triple high-speed Analog-to-Digital Converter 110 Msps  
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Table 17: Characteristics…continued  
VCCA = V11 (or V19, V27 or V99) referenced to AGND (V13, V21, V29 or V96) = 4.75 to 5.25 V; VCCD = V95 referenced to DGND  
(V86) = 4.75 to 5.25 V; VDDD = V40 referenced to VSSD (V41) = 4.75 to 5.25 V; VCCO = V59 (or V69, V79 or V85) referenced to  
OGND (V48, V60, V70 or V82) = 4.75 to 5.25 V; AGND, DGND, OGND and VSSD connected together; Tamb = 0 to 70 °C; typical  
values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
IDDD  
logic supply current for  
I2C-bus and 3-wire serial  
bus  
1.0  
mA  
ICCD  
digital supply current  
40  
26  
5
mA  
mA  
mA  
mA  
ICCO  
output stages supply current ramp input; fclk = 110 MHz  
output PLL supply current  
ICCO(PLL)  
ICCA(PLL)  
VCC  
analog PLL supply current  
28  
supply voltage differences  
VCCA VCCD  
0.25  
+0.25  
+0.25  
V
V
VCCO VCCD  
;
0.25  
VCCO VDDD  
VCCA VDDD  
;
0.25  
+0.25  
V
VCCD VDDD  
VCCA VCCO  
0.25  
+0.25  
V
Ptot  
Ppd  
total power dissipation  
ramp input; fclk = 110 MHz  
1.1  
87  
W
power dissipation in  
Power-down mode  
mW  
R, G and B amplifiers  
B
bandwidth  
3 dB; Tamb = 25 °C  
250  
MHz  
ns  
tset  
settling time of the block  
ADC plus AGC  
full-scale (black-to-white)  
transition; input signal settling  
time <1 ns (1 to 99%);  
Tamb = 25 °C  
4.5  
6
GNCOARSE coarse gain range  
Vref = 2.5 V; minimum coarse  
gain register; code = 32  
(see Figure 6)  
1.67  
dB  
dB  
register; code = 99  
(see Figure 6)  
8
GFINE  
fine gain correction range  
fine register input code = 0  
(see Figure 7)  
0
dB  
fine register input code = 31  
(see Figure 7)  
0.5  
dB  
Gamp/T amplifier gain stability as a Vref = 2.5 V with 100 ppm/°C  
200  
ppm/°C  
function of temperature  
maximum variation  
IGC  
gain current  
±20  
µA  
tstab  
amplifier gain adjustment  
speed  
HSYNC active; capacitors on  
pins 8, 16 and 24 = 22 nF  
25  
mdB/µs  
Vi(p-p)  
input voltage range  
(peak-to-peak value)  
corresponding to full-scale  
output  
0.4  
1.2  
V
tr(Vi)  
tf(Vi)  
input voltage rise time  
input voltage fall time  
fi = 110 MHz; square wave  
fi = 110 MHz; square wave  
2.5  
2.5  
ns  
ns  
9397 750 07338  
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Product specification  
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25 of 38  
 
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
Table 17: Characteristics…continued  
VCCA = V11 (or V19, V27 or V99) referenced to AGND (V13, V21, V29 or V96) = 4.75 to 5.25 V; VCCD = V95 referenced to DGND  
(V86) = 4.75 to 5.25 V; VDDD = V40 referenced to VSSD (V41) = 4.75 to 5.25 V; VCCO = V59 (or V69, V79 or V85) referenced to  
OGND (V48, V60, V70 or V82) = 4.75 to 5.25 V; AGND, DGND, OGND and VSSD connected together; Tamb = 0 to 70 °C; typical  
values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
GE(rms)  
channel-to-channel gain  
matching (RMS value)  
maximum coarse gain;  
Tamb = 25 °C  
1
%
minimum coarse gain;  
2
%
Tamb = 25 °C  
Clamps  
PCLP  
precision  
black level noise on RGB  
channels = 10 mV (max.)  
(RMS value); Tamb = 25 °C  
1  
+1  
LSB  
ns  
tCOR1  
clamp correction time to  
within ±10 mV  
±100 mV black level input  
variation; clamp  
capacitor = 4.7 nF  
300  
10  
tCOR2  
clamp correction time to  
less than 1 LSB  
±100 mV black level input  
variation; clamp  
lines  
capacitor = 4.7 nF  
tW(CLP)  
CLPE  
clamp pulse width  
500  
2000  
+1  
ns  
channel-to-channel clamp  
matching  
1  
LSB  
Aoff  
code clamp reference  
clamp register input code = 0  
63.5  
LSB  
LSB  
clamp register input  
code = 255  
+64  
clamp register input  
code = 367  
+120  
+136  
LSB  
LSB  
clamp register input  
code = 398  
Phase-locked loop  
jPLL(rms)  
maximum PLL phase jitter  
fclk = 110 MHz; see Table 18  
112  
ps  
(RMS value)  
divider ratio  
DR  
fref  
100  
15  
4095  
280  
reference clock frequency  
range  
kHz  
fPLL  
output clock frequency  
range  
12  
110  
MHz  
tCOAST(max) maximum coast mode time  
40  
lines  
lines  
ms  
trecap  
tcap  
PLL recapture time  
PLL capture time  
phase shift step  
when coast mode is aborted  
in start-up conditions  
Tamb = 25 °C  
3
5
Φstep  
ADCs  
fs  
11.25  
deg  
maximum sampling  
frequency  
110  
MHz  
LSB  
INL  
DC integral non-linearity  
from IC analog input to digital  
output; ramp input;  
±0.5  
±1.5  
fclk = 110 MHz  
9397 750 07338  
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Product specification  
Rev. 03 — 21 July 2000  
26 of 38  
 
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
Table 17: Characteristics…continued  
VCCA = V11 (or V19, V27 or V99) referenced to AGND (V13, V21, V29 or V96) = 4.75 to 5.25 V; VCCD = V95 referenced to DGND  
(V86) = 4.75 to 5.25 V; VDDD = V40 referenced to VSSD (V41) = 4.75 to 5.25 V; VCCO = V59 (or V69, V79 or V85) referenced to  
OGND (V48, V60, V70 or V82) = 4.75 to 5.25 V; AGND, DGND, OGND and VSSD connected together; Tamb = 0 to 70 °C; typical  
values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
DNL  
DC differential non linearity from IC analog input to digital  
±0.5  
±1.0  
LSB  
output; ramp input;  
fclk = 110 MHz  
[1]  
ENOB  
effective number of bits  
from IC analog input to digital  
output; 10 kHz sine wave  
input; ramp input;  
7.4  
bits  
fclk = 110 MHz  
Signal-to-noise ratio  
S/N  
signal-to-noise ratio  
maximum gain; fclk = 110 MHz  
minimum gain; fclk = 110 MHz  
45  
44  
dB  
dB  
Spurious free dynamic range  
SFDR  
spurious free dynamic  
range  
maximum gain; fclk = 110 MHz  
minimum gain; fclk = 110 MHz  
60  
60  
dB  
dB  
Clock timing output (CKADCO, CKBO and CKAO)  
ηext  
ADC clock duty cycle  
clock frequency  
100 MHz output  
45  
50  
55  
%
fclk  
110  
MHz  
Clock timing input (CKEXT)  
fclk  
clock frequency  
110  
MHz  
ns  
tCPH  
tCPL  
clock pulse width HIGH  
clock pulse width LOW  
3.6  
4.5  
9.5  
ns  
td(CLKO)  
delay from CKEXT to  
CKADCO  
INV set to LOW  
INV set to HIGH  
10.1  
10.7  
ns  
10.1 + 12tclk  
0.1  
ns  
t-td(CLKO) time difference between  
when operated in the same  
conditions  
0.3  
ns  
[2]  
Data timing (see Figure 11); fclk = 110 MHz; CL = 10 pF;  
td(s)  
td(o)  
th(o)  
sampling delay time  
output delay time  
output hold time  
referenced to CKADCO  
ns  
ns  
ns  
2  
2.3  
1.5  
1.5  
3-state output delay time (see Figure 12)  
tdZH  
tdZL  
tdHZ  
tdLZ  
output enable HIGH  
output enable LOW  
output disable HIGH  
output disable LOW  
12  
10  
50  
65  
ns  
ns  
ns  
ns  
PLL clock output  
VOL  
VOH  
IOL  
LOW-level output voltage  
Io = 1 mA  
0.3  
3.5  
2
0.4  
V
HIGH-level output voltage  
LOW-level output current  
HIGH-level output current  
Io = 1 mA  
VOL = 0.4 V  
VOH = 2.7 V  
2.4  
V
mA  
mA  
IOH  
0.4  
9397 750 07338  
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Product specification  
Rev. 03 — 21 July 2000  
 
27 of 38  
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
Table 17: Characteristics…continued  
VCCA = V11 (or V19, V27 or V99) referenced to AGND (V13, V21, V29 or V96) = 4.75 to 5.25 V; VCCD = V95 referenced to DGND  
(V86) = 4.75 to 5.25 V; VDDD = V40 referenced to VSSD (V41) = 4.75 to 5.25 V; VCCO = V59 (or V69, V79 or V85) referenced to  
OGND (V48, V60, V70 or V82) = 4.75 to 5.25 V; AGND, DGND, OGND and VSSD connected together; Tamb = 0 to 70 °C; typical  
values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
ADC data outputs  
VOL  
VOH  
IOL  
LOW-level output voltage  
Io = 1 mA  
0
0.4  
V
HIGH-level output voltage  
LOW-level output current  
HIGH-level output current  
Io = 1 mA  
VOL = 0.4 V  
VOH = 2.7 V  
2.4  
VCCD  
2
V
mA  
mA  
IOH  
0.4  
TTL digital inputs (CKREF, COAST, CKEXT, INV, HSYNC and CLP)  
VIL  
VIH  
IIL  
LOW-level input voltage  
HIGH-level input voltage  
LOW-level input current  
HIGH-level input current  
input impedance  
0.8  
V
2.0  
400  
V
VIL = 0.4 V  
VIH = 2.7 V  
µA  
µA  
kΩ  
pF  
IIH  
Zi  
100  
4
Ci  
input capacitance  
4.5  
TTL digital inputs (PWDWN, OE)  
VIL  
LOW-level input voltage  
HIGH-level input voltage  
input current pin OE  
0.8  
V
VIH  
2.0  
V
[3]  
[3]  
II(OE)  
II(PWDWN)  
with 10 kresistor  
1.0  
1.0  
mA  
mA  
input current pin PWDWN  
with 10 kresistor  
3-wire serial bus  
trst  
reset time of the chip before  
600  
ns  
3-wire serial bus  
communication  
tsu  
data set-up time  
data hold time  
100  
100  
ns  
ns  
th  
I2C-bus[4]  
fSCL  
clock frequency  
0
100  
kHz  
tBUF  
time the bus must be free  
before new transmission  
can start  
4.7  
µs  
tHD;STA  
tSU;STA  
tCKL  
start condition hold time  
start condition set-up time  
LOW-level clock period  
HIGH-level clock period  
data set-up time  
4.0  
4.7  
4.7  
4.0  
250  
0
µs  
µs  
µs  
µs  
ns  
ns  
µs  
ns  
µs  
pF  
repeated start  
tCKH  
tSU;DAT  
tHD;DAT  
tr  
data hold time  
SDA and SCL rise time  
SDA and SCL fall time  
stop condition set-up time  
bus line capacitive loading  
fSCL = 100 kHz  
fSCL = 100 kHz  
1.0  
300  
tf  
tSU;STOP  
CL(bus)  
4.0  
400  
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Product specification  
Rev. 03 — 21 July 2000  
 
28 of 38  
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
[1] Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental  
period. The calculation takes into account all harmonics and noise up to half clock frequency (NYQUIST frequency).  
Conversion-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.  
[2] Output data acquisition is available after the maximum delay time td(o), which is the time during which the data is available. All the  
timings are given for a 10 pF capacitive load. A higher load can be used but the timing must then be rechecked.  
[3] The input current must be limited in accordance with the limiting values.  
[4] The I2C-bus timings are given for a frequency of 100 kbit/s (100 kHz). This bus can be used at a frequency of 400 kbit/s (400 kHz).  
t
t
CPL  
CPH  
n
50 % = 1.4 V  
CKADCO  
t
d(o)  
DATA  
2.4 V  
1.4 V  
0.4 V  
R0 to R7, ROR  
G0 to G7, GOR  
B0 to B7, BOR  
I
I
I
I
n 1  
n
n + 1  
n + 2  
t
h(o)  
t
d(s)  
V
in  
sample N + 2  
sample N + 1  
FCE475  
sample N  
Fig 11. Data timing diagram.  
OE  
V
CCD  
50%  
t
t
dZH  
dHZ  
HIGH  
90%  
output  
data  
50%  
t
t
dLZ  
LOW  
dZL  
HIGH  
V
CCD  
output  
data  
50%  
S1  
3.3 kΩ  
LOW  
10%  
TDA8752B  
OE  
10 pF  
FCE476  
fOE = 100 kHz; switch S1 connected to VCCD for tdLZ and tdZL; switch S1 connected to GND for tdHZ and tdZH  
.
Fig 12. Timing diagram and test conditions of 3-state output delay time.  
9397 750 07338  
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Product specification  
Rev. 03 — 21 July 2000  
29 of 38  
 
           
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
Table 18: Examples of PLL settings and performance  
VCCA = VDDD = VCCD = VCCO = 5 V; Tamb = 25 °C.  
Video standards  
fref  
fclk  
N
KO  
CZ  
CP  
IP  
Z
Long-term time jitter[1]  
(kHz) (MHz)  
(MHz/V) (nF) (nF) (µA) (k)  
RMS-value  
(ps)  
peak-to-peak  
value (ns)  
CGA: 640 × 200  
VGA: 640 × 480  
VGA: 640 × 482  
15.75 14.3  
912  
15  
20  
20  
39  
39  
39  
39  
0.15 100  
0.15 200  
0.15 400  
0.15 200  
8
4
4
4
593  
255  
173  
200  
3.56  
31.5  
25.18 800  
1.53  
48.07 38.4  
48.08 50  
800  
1.04  
VESA: 800 × 600  
1040 35  
1.2  
(SVGA 72 Hz)  
VESA: 1024 × 768  
60.02 78.75 1312 50  
39  
0.15 700  
2
122  
0.73  
(XGA 75 Hz)  
SUN: 1152 × 900  
66.67 100  
63.98 108  
1500 50  
1688 50  
39  
39  
0.15 400  
0.15 400  
4
4
115  
112  
0.69  
0.67  
VESA: 1280 × 1024  
(SXGA 60 Hz)  
[1] PLL long-term time jitter is measured at the end of the video line, where it is at its maximum.  
9397 750 07338  
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Product specification  
Rev. 03 — 21 July 2000  
30 of 38  
 
   
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
13. Application information  
PWDWN  
CKBO  
150 pF  
CP  
CLP  
OE  
CKADCO  
CCO(PLL)  
39 nF  
CZ  
CCA(PLL)  
n.c.  
COAST  
V
R1 R2  
AGND  
CKEXT  
PLL  
CKREF  
OGND  
CKAO  
V
PLL  
HSYNC  
INV  
DGND  
V
CCD  
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81  
n.c.  
CKREFO  
1
80  
10 nF  
V
DEC2  
CCO(R)  
2
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
V
ref  
R7  
R6  
R5  
R4  
R3  
R2  
R1  
2.5 V  
3
DEC1  
n.c.  
4
1.5 nF  
5
RAGC  
RBOT  
RGAINC  
RCLP  
6
10 nF  
7
22 nF  
10 nF  
100 nF  
8
4.7 nF  
9
RDEC  
R0  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
V
OGND  
V
CCA(R)  
RIN  
R
CCO(G)  
RIN  
GIN  
BIN  
AGND  
R
G7  
75 or 50 Ω  
10 nF  
G6  
G5  
G4  
G3  
G2  
G1  
GAGC  
GBOT  
22 nF  
TDA8752B  
GGAINC  
GCLP  
4.7 nF  
10 nF  
GDEC  
V
CCA(G)  
100 nF  
GIN  
G0  
AGND  
G
OGND  
V
G
75 or 50 Ω  
10 nF  
BAGC  
BBOT  
CCO(B)  
B7  
22 nF  
B6  
B5  
B4  
B3  
B2  
B1  
n.c.  
BGAINC  
BCLP  
4.7 nF  
10 nF  
BDEC  
V
CCA(B)  
BIN  
100 nF  
AGND  
B
75 or 50 Ω  
n.c.  
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
V
n.c.  
ROR BOR  
n.c. GOR  
n.c.  
ADD1 TCK  
ADD2 TDO SEN  
DIS  
B0  
n.c.  
OGND  
DDD  
V
2
SSD  
I C/3W  
B
4.7  
4.7  
FCE477  
kΩ  
kΩ  
SDA  
SCL  
V
V
DDD  
DDD  
All supply pins have to be decoupled, with two capacitors: one for the high frequencies (approximately 1 nF) and one for the low  
frequencies (approximately 100 nF or higher). If a capacitor of 39 nF between pins CZ and CP is not available, use a higher one  
as close as possible to this value. Resistors R1 and R2 must be connected: the recommended value is 10 k.  
Fig 13. Application diagram.  
9397 750 07338  
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Product specification  
Rev. 03 — 21 July 2000  
31 of 38  
 
 
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
14. Package outline  
QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm  
SOT317-2  
y
X
A
80  
51  
81  
50  
Z
E
e
A
2
H
A
E
E
(A )  
3
A
1
θ
w M  
p
pin 1 index  
L
p
b
L
31  
100  
detail X  
1
30  
w M  
Z
v
M
D
A
b
p
e
D
B
H
v
M
B
D
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.  
7o  
0o  
0.25 2.90  
0.05 2.65  
0.40 0.25 20.1 14.1  
0.25 0.14 19.9 13.9  
24.2 18.2  
23.6 17.6  
1.0  
0.6  
0.8  
0.4  
1.0  
0.6  
mm  
3.20  
0.25  
0.65  
1.95  
0.2 0.15 0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
97-08-01  
99-12-27  
SOT317-2  
MO-112  
Fig 14. SOT317-2 package outline.  
9397 750 07338  
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Product specification  
Rev. 03 — 21 July 2000  
 
32 of 38  
 
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
15. Handling information  
Inputs and outputs are protected against electrostatic discharge in normal handling.  
However, to be completely safe, it is desirable to take normal precautions appropriate  
to handling integrated circuits.  
16. Soldering  
16.1 Introduction to soldering surface mount packages  
This text gives a very brief insight to a complex technology. A more in-depth account  
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit  
Packages (document order number 9398 652 90011).  
There is no soldering method that is ideal for all surface mount IC packages. Wave  
soldering can still be used for certain surface mount ICs, but it is not suitable for fine  
pitch SMDs. In these situations reflow soldering is recommended.  
16.2 Reflow soldering  
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and  
binding agent) to be applied to the printed-circuit board by screen printing, stencilling  
or pressure-syringe dispensing before package placement.  
Several methods exist for reflowing; for example, convection or convection/infrared  
heating in a conveyor type oven. Throughput times (preheating, soldering and  
cooling) vary between 100 and 200 seconds depending on heating method.  
Typical reflow peak temperatures range from 215 to 250 °C. The top-surface  
temperature of the packages should preferable be kept below 220 °C for thick/large  
packages, and below 235 °C small/thin packages.  
16.3 Wave soldering  
Conventional single wave soldering is not recommended for surface mount devices  
(SMDs) or printed-circuit boards with a high component density, as solder bridging  
and non-wetting can present major problems.  
To overcome these problems the double-wave soldering method was specifically  
developed.  
If wave soldering is used the following conditions must be observed for optimal  
results:  
Use a double-wave soldering method comprising a turbulent wave with high  
upward pressure followed by a smooth laminar wave.  
For packages with leads on two sides and a pitch (e):  
larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be  
parallel to the transport direction of the printed-circuit board;  
smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the  
transport direction of the printed-circuit board.  
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Product specification  
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TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
The footprint must incorporate solder thieves at the downstream end.  
For packages with leads on four sides, the footprint must be placed at a 45° angle  
to the transport direction of the printed-circuit board. The footprint must  
incorporate solder thieves downstream and at the side corners.  
During placement and before soldering, the package must be fixed with a droplet of  
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the adhesive is cured.  
Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the  
need for removal of corrosive residues in most applications.  
16.4 Manual soldering  
Fix the component by first soldering two diagonally-opposite end leads. Use a low  
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time  
must be limited to 10 seconds at up to 300 °C.  
When using a dedicated tool, all other leads can be soldered in one operation within  
2 to 5 seconds between 270 and 320 °C.  
16.5 Package related soldering information  
Table 19: Suitability of surface mount IC packages for wave and reflow soldering  
methods  
Package  
Soldering method  
Wave  
Reflow[1]  
suitable  
suitable  
BGA, LFBGA, SQFP, TFBGA  
not suitable  
not suitable[2]  
HBCC, HLQFP, HSQFP, HSOP, HTQFP,  
HTSSOP, SMS  
PLCC[3], SO, SOJ  
LQFP, QFP, TQFP  
SSOP, TSSOP, VSO  
suitable  
suitable  
suitable  
suitable  
not recommended[3] [4]  
not recommended[5]  
[1] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the  
maximum temperature (with respect to time) and body size of the package, there is a risk that internal  
or external package cracks may occur due to vaporization of the moisture in them (the so called  
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated  
Circuit Packages; Section: Packing Methods.  
[2] These packages are not suitable for wave soldering as a solder joint between the printed-circuit board  
and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top  
version).  
[3] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave  
direction. The package footprint must incorporate solder thieves downstream and at the side corners.  
[4] Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger  
than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.  
[5] Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than  
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.  
9397 750 07338  
© Philips Electronics N.V. 2000. All rights reserved.  
Product specification  
Rev. 03 — 21 July 2000  
34 of 38  
 
   
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
17. Revision history  
Table 20: Revision history  
Rev Date  
CPCN  
Description  
3
2
1
20000721  
Product specification  
Preliminary specification  
Objective specification  
20000110  
19991111  
9397 750 07338  
© Philips Electronics N.V. 2000. All rights reserved.  
Product specification  
Rev. 03 — 21 July 2000  
35 of 38  
 
 
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
18. Data sheet status  
[1]  
Datasheet status  
Product status Definition  
Development  
Objective specification  
This data sheet contains the design target or goal specifications for product development. Specification may  
change in any manner without notice.  
Preliminary specification Qualification  
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips  
Semiconductors reserves the right to make changes at any time without notice in order to improve design and  
supply the best possible product.  
Product specification  
Production  
This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any  
time without notice in order to improve design and supply the best possible product.  
[1]  
Please consult the most recently issued data sheet before initiating or completing a design.  
customers using or selling these products for use in such applications do so  
at their own risk and agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
19. Definitions  
Short-form specification The data in  
extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
a
short-form specification is  
Right to make changes — Philips Semiconductors reserves the right to  
make changes, without notice, in the products, including circuits, standard  
cells, and/or software, described or contained herein in order to improve  
design and/or performance. Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no  
licence or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products  
are free from patent, copyright, or mask work right infringement, unless  
otherwise specified.  
Limiting values definition Limiting values given are in accordance with  
the Absolute Maximum Rating System (IEC 60134). Stress above one or  
more of the limiting values may cause permanent damage to the device.  
These are stress ratings only and operation of the device at these or at any  
other conditions above those given in the Characteristics sections of the  
specification is not implied. Exposure to limiting values for extended periods  
may affect device reliability.  
Application information Applications that are described herein for any  
of these products are for illustrative purposes only. Philips Semiconductors  
make no representation or warranty that such applications will be suitable for  
the specified use without further testing or modification.  
21. Licenses  
Purchase of Philips I2C components  
Purchase of Philips I2C components conveys a license  
under the Philips’ I2C patent to use the components in the  
I2C system provided the system conforms to the I2C  
specification defined by Philips. This specification can be  
ordered using the code 9398 393 40011.  
20. Disclaimers  
Life support — These products are not designed for use in life support  
appliances, devices, or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors  
9397 750 07338  
© Philips Electronics N.V. 2000 All rights reserved.  
Product specification  
Rev. 03 — 21 July 2000  
 
36 of 38  
         
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
Philips Semiconductors - a worldwide company  
Argentina: see South America  
Netherlands: Tel. +31 40 278 2785, Fax. +31 40 278 8399  
Australia: Tel. +61 2 9704 8141, Fax. +61 2 9704 8139  
Austria: Tel. +43 160 101, Fax. +43 160 101 1210  
Belarus: Tel. +375 17 220 0733, Fax. +375 17 220 0773  
Belgium: see The Netherlands  
New Zealand: Tel. +64 98 49 4160, Fax. +64 98 49 7811  
Norway: Tel. +47 22 74 8000, Fax. +47 22 74 8341  
Philippines: Tel. +63 28 16 6380, Fax. +63 28 17 3474  
Poland: Tel. +48 22 5710 000, Fax. +48 22 5710 001  
Portugal: see Spain  
Brazil: see South America  
Bulgaria: Tel. +359 268 9211, Fax. +359 268 9102  
Canada: Tel. +1 800 234 7381  
Romania: see Italy  
Russia: Tel. +7 095 755 6918, Fax. +7 095 755 6919  
Singapore: Tel. +65 350 2538, Fax. +65 251 6500  
Slovakia: see Austria  
China/Hong Kong: Tel. +852 2 319 7888, Fax. +852 2 319 7700  
Colombia: see South America  
Czech Republic: see Austria  
Slovenia: see Italy  
Denmark: Tel. +45 3 288 2636, Fax. +45 3 157 0044  
Finland: Tel. +358 961 5800, Fax. +358 96 158 0920  
France: Tel. +33 14 099 6161, Fax. +33 14 099 6427  
Germany: Tel. +49 40 23 5360, Fax. +49 402 353 6300  
Hungary: see Austria  
South Africa: Tel. +27 11 471 5401, Fax. +27 11 471 5398  
South America: Tel. +55 11 821 2333, Fax. +55 11 829 1849  
Spain: Tel. +34 33 01 6312, Fax. +34 33 01 4107  
Sweden: Tel. +46 86 32 2000, Fax. +46 86 32 2745  
Switzerland: Tel. +41 14 88 2686, Fax. +41 14 81 7730  
Taiwan: Tel. +886 22 134 2451, Fax. +886 22 134 2874  
Thailand: Tel. +66 23 61 7910, Fax. +66 23 98 3447  
Turkey: Tel. +90 216 522 1500, Fax. +90 216 522 1813  
Ukraine: Tel. +380 44 264 2776, Fax. +380 44 268 0461  
United Kingdom: Tel. +44 208 730 5000, Fax. +44 208 754 8421  
United States: Tel. +1 800 234 7381  
India: Tel. +91 22 493 8541, Fax. +91 22 493 8722  
Indonesia: see Singapore  
Ireland: Tel. +353 17 64 0000, Fax. +353 17 64 0200  
Israel: Tel. +972 36 45 0444, Fax. +972 36 49 1007  
Italy: Tel. +39 039 203 6838, Fax +39 039 203 6800  
Japan: Tel. +81 33 740 5130, Fax. +81 3 3740 5057  
Korea: Tel. +82 27 09 1412, Fax. +82 27 09 1415  
Malaysia: Tel. +60 37 50 5214, Fax. +60 37 57 4880  
Mexico: Tel. +9-5 800 234 7381  
Uruguay: see South America  
Vietnam: see Singapore  
Yugoslavia: Tel. +381 11 3341 299, Fax. +381 11 3342 553  
Middle East: see Italy  
For all other countries apply to: Philips Semiconductors,  
Marketing Communications,  
Building BE, P.O. Box 218, 5600 MD EINDHOVEN,  
The Netherlands, Fax. +31 40 272 4825  
(SCA70)  
9397 750 07338  
© Philips Electronics N.V. 2000. All rights reserved.  
Product specification  
Rev. 03 — 21 July 2000  
 
37 of 38  
TDA8752B  
Triple high-speed Analog-to-Digital Converter 110 Msps  
Philips Semiconductors  
General description . . . . . . . . . . . . . . . . . . . . . . 1  
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2  
Ordering information. . . . . . . . . . . . . . . . . . . . . 3  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 7  
Functional description . . . . . . . . . . . . . . . . . . 11  
Clamps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Variable gain amplifiers . . . . . . . . . . . . . . . . . 11  
ADC outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Phase-locked loop . . . . . . . . . . . . . . . . . . . . . 13  
I2C-bus and 3-wire serial bus interface. . . . . . 16  
I2C-bus and 3-wire serial bus interfaces . . . . 17  
Register definitions . . . . . . . . . . . . . . . . . . . . . 17  
Offset register . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Coarse and fine registers . . . . . . . . . . . . . . . . 18  
Control register . . . . . . . . . . . . . . . . . . . . . . . . 19  
VCO register. . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Divider register . . . . . . . . . . . . . . . . . . . . . . . . 21  
Power-down mode . . . . . . . . . . . . . . . . . . . . . 21  
PHASEA and PHASEB registers . . . . . . . . . . 21  
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 22  
3-wire serial bus protocol . . . . . . . . . . . . . . . . 23  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 24  
Thermal characteristics. . . . . . . . . . . . . . . . . . 24  
Application information. . . . . . . . . . . . . . . . . . 31  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 32  
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 33  
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 34  
20  
21  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 35  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 36  
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
© Philips Electronics N.V. 2000.  
Printed in The Netherlands  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior  
written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or  
contract, is believed to be accurate and reliable and may be changed without notice. No  
liability will be accepted by the publisher for any consequence of its use. Publication  
thereof does not convey nor imply any license under patent- or other industrial or  
intellectual property rights.  
Date of release: 21 July 2000  
Document order number: 9397 750 07338  
 

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